Power semiconductor products are often fabricated using N or P channel drain-extended metal-oxide-semiconductor (DEMOS) transistor devices for high power switching applications. DEMOS devices advantageously combine short-channel operation with high current handling capabilities, relatively low drain-to-source on-state resistance (Rdson), and the ability to withstand high blocking voltages without suffering voltage breakdown failure (high breakdown voltage ratings). Breakdown voltage is typically measured as drain-to-source breakdown voltage with the gate and source shorted together (BVdss), where DEMOS device designs often involve a tradeoff between breakdown voltage BVdss and Rdson.
Referring to FIG. 1A a conventional drain extended PMOS control transistor CT1 is illustrated in an integrated circuit or semiconductor device 2 with a p-type drain 24 spaced from a gate 14, 16 having sidewall spacers 20. The transistor CT1 is formed in a p-doped silicon substrate 4 (P+) with a lower epitaxial silicon 4a (P-lower epi) formed over the substrate 4, where a p-type upper epitaxial silicon 6 (upper epi) is formed over the lower EPI 4a, and an n-buried layer 8 (NBL) extends in an upper portion of the lower EPI 4a and a lower portion of the upper EPI 6. An N-WELL 12 is formed in an upper portion of the upper EPI 6, leaving a p-type drift region 6a outside the N-WELL 12, and various field oxide (FOX) isolation structures 10 are formed to separate different terminals of the transistor CT1 from one another and from other components in the integrated circuit device 2.
A p-type source (S) 22 is formed in the N-WELL 12 along one side of a channel region 28 of the N-WELL 12, and an n-type backgate (BG) 26, in the illustrated example, is spaced from the source 22 in the N-WELL 12. A p-type extended drain (D) 24 is formed in the drift region 6a, and is spaced from the other side of the channel 28. The transistor gate structure (G) includes a thin gate dielectric or gate oxide 14 formed over the channel region 28 of the N-WELL 12, which also partially overlies a portion of the p-drift region 6a, with a conductive gate electrode 16 formed over the thin gate oxide 14 and sidewall spacers 20 formed along the lateral sides of the gate (G).
FIG. 1B is a schematic illustration of an exemplary high voltage application in which the conventional DEPMOS CT1 of FIG. 1A is employed as a control transistor for driving the gate of a bridge high-side driver DENMOS. FIG. 1B illustrates a half H-bridge driver circuit in the semiconductor device 2 powered by a DC supply voltage VCC, with the conventional DEPMOS control transistor CT1 of FIG. 1A and a DENMOS control transistor CT2 together forming an inverter for controlling a gate voltage of a high-side DENMOS drive transistor T2 in the half bridge circuit. The circuit includes two load driving n-channel power devices such as DENMOS or LDMOS (lateral diffused MOS) devices T1 and T2 having corresponding sources S1 and S2, drains D1 and D2, and gates G1 and G2, respectively, coupled to drive an inductive load. The transistors T1 and T2 are arranged as a pair of low and high-side drivers, respectively, with the load coupled between an intermediate node N1 of the driver pair and ground.
A supply voltage VCC is coupled to the drain D2 of the high-side driver T2, and can be a positive terminal of a battery source, wherein the ground may be the battery negative terminal, for example, in automotive applications. The low-side driver T1 and the high-side driver T2 are coupled in series between the supply voltage VCC and ground, where the high side driver transistor T2 has a drain D2 coupled to VCC and a source S2 coupled with the intermediate node N1 at the load. The low-side transistor T1 has a drain D1 coupled to the node N1 and a source S1 coupled to ground. The intermediate node N1 between the transistors T1 and T2 is coupled to a first terminal of a load and the other load terminal is coupled to ground, wherein the load is typically not a part of the device 2. The low and high side transistor gates G1 and G2 are controlled so as to drive the load in alternating fashion, wherein an inverter CT1, CT2 (including the DEPMOS transistor CT1 of FIG. 1A) is illustrated to drive the high-side gate G2. When the high-side transistor T2 is on, current flows through the high-side transistor T2 and the load in a first direction, and when the low-side transistor T1 is on, current flows through the load and the low-side transistor T1 in a second opposite direction.
In the illustrated device 2, the source S of the DEPMOS control transistor CT1 is coupled to a high voltage VCC+VGS, where VGS is the gate-to-source voltage required to turn the high-side device T2 on, and VCC is the supply voltage. In this configuration, the upper control transistor CT1 must be designed to withstand high drain-to-source voltages without breakdown when the upper control transistor CT1 is off and the lower control transistor CT2 is on. In this condition, the drain D of the transistor CT1 is essentially at ground potential, while the source S remains at VCC+VGS. In automotive and other applications in which bridge driver circuits are used for high wattage digital audio equipment or in other high power circuits, the supply voltage VCC can be very high, such as 65 to 80 volts DC, wherein the driver devices T1 and T2 need to withstand drain-to-source voltages of about VCC without breakdown. Furthermore, the DEPMOS control transistor CT1 needs to withstand even higher drain-to-source voltages, since the drain D of the upper control transistor CT1 may be near ground potential when the lower control transistor CT2 is on. In particular, the VGS of the high-side driver transistor T2 may be 5 to 15 volts DC, wherein the off-state drain-to-source voltage across the DEPMOS transistor CT1 may be 100 volts or more.
As shown in FIG. 1A, the drain region 24 is spaced from the channel 28 and from the gate 14, 16 (e.g., an extended-drain architecture) to provide the drift region 6a in the p-type epitaxial silicon 6 between the channel 28 and the drain 24. In operation, the spacing of the drain 24 and the channel 28 spreads out the electric fields, thereby increasing the breakdown voltage rating of the device (higher BVdss). However, the drain extension increases the resistance of the drain-to-source current path (Rdson), whereby DEMOS device designs often involve a tradeoff between high breakdown voltage BVdss and low Rdson.
Another breakdown voltage limitation of the transistor CT1 relates to the thickness of the epitaxial silicon 6 in the device 2, wherein the substrate 4 is grounded and the transistor source, drain, and channel (e.g., including the N-WELL 12 and the p-drift region 6a) are formed in the epitaxial silicon 6. In particular, when the control transistor CT1 is on, the drain voltage is very high, and it is desirable to separate the p-type drain 24 and the drift region 6a from the underlying p-type substrate 4 that is grounded, to prevent punch-thru current between the drain 24 and the substrate 4. Accordingly, a rather heavily doped n-buried layer 8 is typically formed prior to forming the upper epitaxial silicon layer 6, in order to separate the drift region 6a and the drain 24 from the substrate 4, and to thereby inhibit on-state punch-thru current, with the n-buried layer 8 typically being connected to the n-type backgate 26 through the N-WELL 12, whereby the n-buried layer 8 is tied to the source voltage (VCC+VGS). However, the presence of the n-buried later at such a high voltage may lead to off-state breakdown when the drain 24 is near ground potential. Thus, while the n-buried layer 8 operates to prevent on-state punch-thru current, the n-buried layer 8 limits the off-state breakdown voltage rating of the DEPMOS transistor CT1 for a given epitaxial thickness and drift region doping amount.
In an “off” state of the transistor CT1, the drain 24 is essentially at ground, and the source voltage VCC+VGS is dropped across the drift region 6a portion extending between the bottom of the drain 24 and the n-buried layer 8, and also between the channel-side of the drift region 6a and the drain 24. If the breakdown occurs on the surface between the gate 16 and the p-type drain 24, the lateral extension of the drift region 6a can be increased (e.g., the lateral spacing of the drain 24 from the gate 16 may be increased to prevent lateral breakdown). However, the vertical spacing between the bottom of the p-type drain 24 and the n-buried layer 8 is more difficult to increase. One approach is to increase the thickness of the epitaxial silicon layer 6, wherein a thicker layer 6 allows a deeper drift region 6a to support higher voltages without suffering breakdown. However, increasing the epitaxial thickness is costly in terms of process complexity, larger spacing requirements, and larger design rules, particularly in forming the deep diffusions to connect to the n-buried layer 8 or other buried layers in the device 2. Accordingly, there is a need for improved DEPMOS devices and fabrication methods by which increased voltage breakdown withstanding capabilities can be achieved, without increasing epitaxial silicon thicknesses and without sacrificing device performance.